Exemplary embodiments of the present invention relate to a non-volatile memory device and a method for fabricating the same, and more particularly, to a non-volatile memory device having a three-dimensional structure and a vertical channel structure.
A non-volatile memory device retains data even when power is interrupted. As a memory device having a two-dimensional structure in which memory cells are arranged on a silicon substrate in a single layer reaches a limit in improving the integration density of the memory device, a non-volatile memory device having a three-dimensional structure in which memory cells are vertically stacked on a silicon substrate has been proposed.
A method for fabricating a conventional non-volatile memory device having a three-dimensional structure will be described below in detail with reference to FIG. 1.
FIG. 1 is a cross-sectional view illustrating a conventional non-volatile memory device having a three-dimensional structure. Specifically, FIG. 1 illustrates a non-volatile memory device having a three-dimensional structure and a vertical channel structure.
Referring to FIG. 1, the conventional non-volatile memory device having the vertical channel structure includes a lower select transistor (LST), a plurality of memory cells (MC) and an upper select transistor (UST) sequentially stacked above a substrate 10 along a channel vertically protruding from the substrate 10. Thus, a string is vertically arranged on the substrate 10.
Also, the conventional non-volatile memory device includes a common source region doped with an N-type impurity in the substrate 10. A plurality of strings composing a memory block are connected to the common source region in parallel. Specifically, a channel doped with an N-type impurity is connected to the common source region doped with the N-type impurity.
A method for fabricating the conventional non-volatile memory device having the three-dimensional structure will be described below in detail.
A source region is formed by doping an impurity into the substrate 10. A plurality of inter-layer dielectric layers 11 and a plurality of conductive layers 12 for gate electrodes are alternately formed on the substrate 10 in which the source region is formed.
The inter-layer dielectric layers 11 and the conductive layers 12 for gate electrodes are selectively etched to form a trench which exposes the surface of the substrate 10, and an insulation layer is formed inside of the trench. For example, when the lower select transistor and the upper select transistor are formed, a gate insulation layer 13A is formed on the inner wall of the trench. When the memory cells are formed, a charge blocking layer, a charge trap layer, and a tunnel insulation layer 13B are sequentially formed on the inner wall of the trench.
The trench having the gate insulation layer 13A or the charge blocking layer, the charge trap layer, and the tunnel insulation layer 13B is filled with a layer for a channel to form a channel (CH). Thus, a lower select transistor (LST), a plurality of memory cells (MC) and an upper select transistor (UST) are sequentially formed over the substrate 10 along the channel CH vertically protruding from the substrate 10.
However, according to the method for fabricating the conventional non-volatile memory device, it is impossible to fabricate a non-volatile memory device having the memory cells operating in an enhancement-mode due to the limitations of the fabrication processes.
In the conventional non-volatile memory device having the three-dimensional structure, the memory cells stacked along the channel protrude vertically from the substrate 10. Herein, the channel is formed by etching the inter-layer dielectric layers 11 and the conductive layers 12 to form the trench, and filling the trench with the layer for a channel. Thus, it is impossible to form a junction, i.e., source/drain region, in the channel between the memory cells.
In the conventional non-volatile memory device, the source region doped with the N-type impurities is formed in the substrate 10, and the channel doped with the N-type impurities forms the memory cells operating in a depletion mode.
Meanwhile, the memory cells operating in the depletion mode process elimination operations by providing holes through a gate induced drain leakage (GIRL) effect in the source region of the lower select transistor. If an insufficient amount of holes are provided, the speed of the elimination operations is lowered. Specifically, since the string is vertically arranged on the substrate 10, the length of the channel is increased, and the supply of the holes becomes difficult. Thus, the speed of the elimination operations is degraded. As a result, the performance of the non-volatile memory device is reduced.